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K4S560432J K4S560832J K4S561632J
Synchronous DRAM
256Mb J-die SDRAM Specification
54 TSOP-II with Lead-Free & Halogen-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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Synchronous DRAM
Table of Contents
1.0 Features ....................................................................................................................................... 4 2.0 General Description ................................................................................................................... 4 3.0 Ordering Information .................................................................................................................. 4 4.0 Package Physical Dimension ................................................................................................... 5 5.0 Functional Block Diagram......................................................................................................... 6 6.0 Pin Configuration (Top view) ..................................................................................................... 7 7.0 Pin Function Description ........................................................................................................... 7 8.0 Absolute Maximum Ratings........................................................................................................8 9.0 DC Operating Conditions ........................................................................................................... 8 10.0 Capacitance............................................................................................................................... 8 11.0 DC Characteristics (x4, x8) ......................................................................................................9 12.0 DC Characteristics (x16) ........................................................................................................10 13.0 AC Operating Test Conditions ...............................................................................................11 14.0 Operating AC Parameter ........................................................................................................11 15.0 AC Characteristics ..................................................................................................................12 16.0 DQ Buffer Output Drive Characteristics ...............................................................................12 17.0 IBIS Specification .....................................................................................................................13 18.0 Simplified Truth Table ............................................................................................................15
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Month June October January March August Year 2007 2007 2008 2008 2008 - Release 1.0 version SPEC - Changed IDD current SPEC - Revised typo of package dimension - Added the comment of Halogen-free supporting - Added 200Mhz speed - Added Package pin out lead width - Added 200MHz current SPEC - Corrected font format History
Revision History
Revision 1.0 1.1 1.2 1.21 1.22
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Synchronous DRAM
16M x 4Bit x 4 Banks / 8M x 8Bit x 4 Banks / 4M x 16Bit x 4 Banks SDRAM 1.0 Features
* * * * JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock. Burst read single-bit write operation DQM (x4,x8) & L(U)DQM (x16) for masking Auto & self refresh 64ms refresh period (8K Cycle) Lead-Free & Halogen-Free Package RoHS compliant
* * * * * * *
2.0 General Description
The K4S560432J / K4S560832J / K4S561632J is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 16,777,216 words by 4 bits / 4 x 8,388,608 words by 8bits / 4 x 4,194,304 words by 16bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
3.0 Ordering Information
Part No. K4S560432J-U*1C/L75 K4S560832J-UC/L75 K4S561632J-UC/L50 K4S561632J-UC/L60 K4S561632J-UC/L75 16M x 16 Orgainization 64M x 4 32M x 8 Max Freq. 133MHz (CL=3) 133MHz (CL=3) 200MHz (CL=3) 166MHz (CL=3) 133MHz (CL=3) LVTTL 54pin TSOP(II) Lead-Free & Halogen-Free*1 Interface Package
Note 1 : 256Mb J-die SDR DRAMs support Lead-Free & Halogen-Free package with Lead-Free package code(-U).
Organization 64Mx4 32Mx8 16Mx16
Row Address A0~A12 A0~A12 A0~A12
Column Address A0-A9, A11 A0-A9 A0-A8
Row & Column address configuration
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4.0 Package Physical Dimension
(0.80) (0.50) #54 #28
Unit : mm
10.16 0.10
(1.50)
(0.80)
0.665 0.05
0.210 0.05
1.00 0.10
22.22 0.10
(R
0.1 5)
(10)
1.20 MAX
0.125 - 0.035
+0.075
(0.50)
#1 (1.50)
#27
(10)
(10)
11.76 0.20
(10.76)
0.05 MIN
0. 15 )
(0.71)
0.80TYP [0.80 0.08]
(R
0.075 MAX
0. 25 )
(R
(R
0. 25 )
Detail A
Detail B
NOTE 1. ( ) IS REFERENCE 2. [ ] IS ASS'Y OUT QUALITY
Detail A
0.30 - 0.05
+0.10
Detail B
(0 8) 0.35 - 0.05
+0.10
54Pin TSOP(II) Package Dimension
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[
(10)
[
(4)
0.10 MAX
Rev. 1.22 August 2008
0.45 ~ 0.75 0.25TYP
K4S560432J K4S560832J K4S561632J
Synchronous DRAM
5.0 Functional Block Diagram
I/O Control
LWE LDQM
Data Input Register Bank Select 16M x 4 / 8M x 8 / 4M x 16 16M x 4 / 8M x 8 / 4M x 16 16M x 4 / 8M x 8 / 4M x 16 16M x 4 / 8M x 8 / 4M x 16 Refresh Counter
Output Buffer
Row Decoder
Sense AMP
Row Buffer
DQi
Address Register
CLK ADD
Column Decoder Col. Buffer Latency & Burst Length Programming Register
LRAS
LCBR
LCKE LRAS LCBR LWE LCAS Timing Register
LWCBR
LDQM
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
* Samsung Electronics reserves the right to change products or specification without notice.
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x16 x8 x4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
6.0 Pin Configuration (Top view)
x4
VSS N.C VSSQ N.C DQ3 VDDQ N.C N.C VSSQ N.C DQ2 VDDQ N.C VSS N.C/RFU DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS
x8
VSS DQ7 VSSQ N.C DQ6 VDDQ N.C DQ5 VSSQ N.C DQ4 VDDQ N.C VSS N.C/RFU DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS
x16
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS N.C/RFU UDQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS
VDD VDD VDD DQ0 DQ0 N.C VDDQ VDDQ VDDQ DQ1 N.C N.C DQ2 DQ1 DQ0 VSSQ VSSQ VSSQ DQ3 N.C N.C DQ4 DQ2 N.C VDDQ VDDQ VDDQ DQ5 N.C N.C DQ6 DQ3 DQ1 VSSQ VSSQ VSSQ DQ7 N.C N.C VDD VDD VDD LDQM N.C N.C WE WE WE CAS CAS CAS RAS RAS RAS CS CS CS BA0 BA0 BA0 BA1 BA1 BA1 A10/AP A10/AP A10/AP A0 A0 A0 A1 A1 A1 A2 A2 A2 A3 A3 A3 VDD VDD VDD
54Pin TSOP (400mil x 875mil) (0.8 mm Pin pitch)
7.0 Pin Function Description
Pin CLK CS CKE Name System clock Chip select Clock enable Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA12, Column address : (x4 : CA0 ~ CA9,CA11), (x8 : CA0 ~ CA9), (x16 : CA0 ~ CA8) Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. Data inputs/outputs are multiplexed on the same pins. (x4 : DQ0 ~ 3), (x8 : DQ0 ~ 7), (x16 : DQ0 ~ 15) Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device.
A0 ~ A12 BA0 ~ BA1 RAS CAS WE DQM DQ0 ~ N VDD/VSS VDDQ/VSSQ N.C/RFU
Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask Data input/output Power supply/ground Data output power/ground No connection /reserved for future use
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Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1 50 Unit V V C W mA
8.0 Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Storage temperature Power dissipation Short circuit current
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
9.0 DC Operating Conditions
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70C) Parameter Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Symbol VDD, VDDQ VIH VIL VOH VOL ILI Min 3.0 2.0 -0.3 2.4 -10 Typ 3.3 3.0 0 Max 3.6 VDD+0.3 0.8 0.4 10 Unit V V V V V uA 1 2 IOH = -2mA IOL = 2mA 3 Note
Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
10.0 Capacitance
Pin Clock RAS, CAS, WE, CS, CKE, DQM Address (x4 : DQ0 ~ DQ3), (x8 : DQ0 ~ DQ7), (x16 : DQ0 ~ DQ15) CCLK CIN CADD COUT
(VDD = 3.3V, TA = 23C, f = 1MHz, VREF =1.4V 200 mV) Symbol Min 2.5 2.5 2.5 4.0 Max 3.5 3.8 3.8 6.0 Unit pF pF pF pF
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(Recommended operating condition unless otherwise noted, TA = 0 to 70C) Test Condition Burst length = 1 tRC tRC(min) IO = 0 mA CKE VIL(max), tCC = 10ns CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 10ns CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IO = 0 mA Page burst 4banks Activated. tCCD = 2CLKs tRC tRC(min) CKE 0.2V C L Version 75 70 2 2 15 mA 10 5 5 28 20 mA mA mA Unit Note
11.0 DC Characteristics (x4, x8)
Parameter Operating current (One bank active) Precharge standby current in power-down mode Symbol
ICC1 ICC2P
mA
1
ICC2PS CKE & CLK VIL(max), tCC = ICC2N ICC2NS ICC3P
mA
Precharge standby current in non power-down mode
Active standby current in power-down mode Active standby current in non power-down mode (One bank active)
ICC3PS CKE & CLK VIL(max), tCC = ICC3N ICC3NS
Operating current (Burst mode) Refresh current Self refresh current
ICC4
110
mA
1
ICC5 ICC6
160 3 1.5
mA mA mA
2 3 4
Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S5604(08)32J-UC 4. K4S5604(08)32J-UL 5. Unless otherwise noticed, input swing level is CMOS(VIH /VIL=VDDQ/VSSQ).
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12.0 DC Characteristics (x16)
(Recommended operating condition unless otherwise noted, TA = 0 to 70C) Parameter Operating current (One bank active) Precharge standby current in power-down mode Symbol Burst length = 1 tRC tRC(min) IO = 0 mA CKE VIL(max), tCC = 10ns CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 10ns CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IO = 0 mA Page burst 4banks Activated. tCCD = 2CLKs tRC tRC(min) CKE 0.2V C L 140 200 Test Condition Version 50 110 60 90 2 2 15 10 5 5 28 20 mA mA mA 75 70 Unit Note
ICC1 ICC2P
mA
1
ICC2PS CKE & CLK VIL(max), tCC = ICC2N ICC2NS ICC3P
mA mA
Precharge standby current in non power-down mode
Active standby current in power-down mode Active standby current in non power-down mode (One bank active)
ICC3PS CKE & CLK VIL(max), tCC = ICC3N ICC3NS
Operating current (Burst mode) Refresh current Self refresh current
ICC4 ICC5 ICC6
120 180 3 1.5
110 160
mA mA mA mA
1 2 3 4
Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S561632J-UC 4. K4S561632J-UL 5. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).
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(VDD = 3.3V 0.3V, TA = 0 to 70C) Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2
3.3V VTT = 1.4V
13.0 AC Operating Test Conditions
Parameter AC input levels (VIH/VIL) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition
Unit V V ns V
1200 Output 870 50pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Z0 = 50
50
50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
14.0 Operating AC Parameter
Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data Symbol tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 CAS latency=2 55 50 (x16 only) 10 15 15 37.5
(AC operating conditions unless otherwise noted) Version 60 (x16 only) 12 18 18 42 100 60 2 2 CLK + tRP 1 1 1 2 1 65 75 15 20 20 45 Unit ns ns ns ns us ns CLK CLK CLK CLK ea 1 2,5 5 2 2 3 4 Note 1 1 1 1
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP. 6. tRC =tRFC, tRDL = tWR.
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(AC operating conditions unless otherwise noted) Symbol CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 tCC tSAC tOH tCH tCL tSS tSH tSLZ CAS latency=3 CAS latency=2 tSHZ 50 (x16 only) Min 5 2 2 2 1.5 1 1 Max 1000 4.5 4.5 2.5 2.5 2.5 1.5 1 1 5 60(x16 only) Min 6 Max 1000 5 3 3 2.5 2.5 1.5 0.8 1 5.4 6 Min 7.5 10 75 Max 1000 5.4 6 Unit ns ns ns ns ns ns ns ns ns Note 1 1,2 2 3 3 3 3 2
15.0 AC Characteristics
Parameter CLK cycle time CLK to valid output delay Output data hold time CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z
Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. 4. tSS applies for address setup time, clock enable setup time. commend setup time and data setup time tSH applies for address holde time, clock enable hold time. commend hold time and data hold time
16.0 DQ Buffer Output Drive Characteristics
Parameter Output rise time Output fall time Output rise time Output fall time Symbol trh tfh trh tfh Condition Measure in linear region : 1.2V ~ 1.8V Measure in linear region : 1.2V ~ 1.8V Measure in linear region : 1.2V ~ 1.8V Measure in linear region : 1.2V ~ 1.8V Min 1.37 1.30 2.8 2.0 3.9 2.9 Typ Max 4.37 3.8 5.6 5.0 Unit Volts/ns Volts/ns Volts/ns Volts/ns Notes 3 3 1,2 1,2
Notes : 1. Rise time specification based on 0pF + 50 to VSS, use these values to design to. 2. Fall time specification based on 0pF + 50 to VDD, use these values to design to. 3. Measured into 50pF only, use these values to characterize to. 4. All measurements done with respect to VSS.
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200MHz/166MHz/133MHz Pull-up
17.0 IBIS Specification
IOH Characteristics (Pull-up)
Voltage (V) 3.45 3.3 3.0 2.6 2.4 2.0 1.8 1.65 1.5 1.4 1.0 0.0 166MHz 133MHz Min I (mA) 166MHz 133MHz Max I (mA) -2.4 -27.3 -74.1 -129.2 -153.3 -197.0 -226.2 -248.0 -269.7 -284.3 -344.5 -502.4 0 0 -100 -200 mA -300 -400 -500 -600 Voltage
IOH Min (200MHz/166MHz/133MHz) IOH Max (200MHz/166MHz/133MHz)
0.5
1
1.5
2
2.5
3
3.5
0.0 -21.1 -34.1 -58.7 -67.3 -73.0 -77.9 -80.8 -88.6 -93.0
200MHz/166MHz/133MHz Pull-down
IOL Characteristics (Pull-down)
Voltage (V) 0.0 0.4 0.65 0.85 1.0 1.4 1.5 1.65 1.8 1.95 3.0 3.45 166MHz 133MHz Min I (mA) 0.0 27.5 41.8 51.6 58.0 70.7 72.9 75.4 77.0 77.6 80.3 81.4 166MHz 133MHz Max I (mA) 0.0 70.2 107.5 133.8 151.2 187.7 194.4 202.5 208.6 212.0 219.6 222.6
250
200
150 mA 100 50 0 0 0.5 1 1.5 2 2.5 3 3.5 Voltage
IOL Min (200MHz/166MHz/133MHz) IOL Max (200MHz/166MHz/133MHz)
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VDD Clamp @ CLK, CKE, CS, DQM & DQ
VDD (V) 0.0 0.2 0.4 0.6 0.7 0.8 0.9 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 I (mA) 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.23 1.34 3.02 5.06 7.35 9.83 12.48 15.30 18.31 20
Minimum VDD clamp current (Referenced to VDD)
15
mA
10
5
0 0 1 Voltage
I (mA)
2
3
Minimum VSS clamp current
VSS Clamp @ CLK, CKE, CS, DQM & DQ
VSS (V) -2.6 -2.4 -2.2 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.9 -0.8 -0.7 -0.6 -0.4 -0.2 0.0 I (mA) -57.23 -45.77 -38.26 -31.22 -24.58 -18.37 -12.56 -7.57 -3.37 -1.75 -0.58 -0.05 0.0 0.0 0.0 0.0 0 -10 -20 mA -30 -40 -50 -60
-3
-2
-1
0
Voltage
I (mA)
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(V=Valid, X=Don't care, H=Logic high, L=Logic low)
CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP A0 ~ A9 A11, A12 Note
18.0 Simplified Truth Table
Command Register Mode register set Auto refresh Refresh Self refresh Entry Exit H H L H H H H Bank selection All banks Entry Exit Entry Precharge power down mode Exit DQM No operation command L H H X H L H H H L H X H L H X X X X X L H L L L L H L L L L L H L X H L H L L L H X L H H H L X V X X H X V X X H X H L L H X H L L H H X V X X H X V
L H H X H H L L L X V X X H X V X H
X X X X X X X X X X X V X V V V
OP code X X Row address L H L H X L H X X
Column address Column address
1,2 3 3 3 3 4 4,5 4 4,5 6
Bank active & row addr. Read & column address Write & column address Burst stop Precharge Clock suspend or active power down Auto precharge disable Auto precharge enable Auto precharge disable Auto precharge enable
X X V X X X 7
Notes : 1. OP Code : Operand code A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
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